Authors - Arunima Saxena, Arindam Bhattacharyya, Lilian Molina, Savita Patil, Hussain Al-Asaad Abstract - Reliable interrupt handling is crucial in embedded systems, especially for real-time applications running on RISC-V architectures. This paper presents a modular and scalable verification methodology for evaluating external interrupt handling in the NEORV32 RISC-V processor. NEORV32 offers a rich trade-off between performance and resource usage, along with strong execution safety features and a flexible software framework - making it an ideal candidate for interrupt verification studies. To thoroughly test the processor’s interrupt logic, we built a custom simulation environment in ModelSim, encapsulating both the core and top-level architecture into reusable libraries. Our primary focus was the External Interrupt Controller (XIRQ), which supports 32 external interrupt channels with various triggering modes. Three targeted test scenarios were developed: a baseline interrupt case, an edge case stressing maximum bit values, and a rising edge-triggered case. Results from these simulations confirm consistent and reliable interrupt handling behavior across all test cases, with uniform response time and correct signal acknowledgment. This work provides practical insights for embedded system designers implementing interrupt-driven applications on RISC-V platforms and establishes a foundation for verifying other modules of NEORV32 in future work.
